As is well known, a flash memory is a non-volatile memory. After the flash memory is powered off, the stored data are still retained in the flash memory. Consequently, the flash memory is widely used in a variety of electronic products.
Generally, the memory array of the flash memory comprises plural memory cells. In addition, each memory cell has a floating gate transistor.
During a program cycle, hot carriers are selectively injected into a floating gate of the floating gate transistor. For example, if no hot carriers are injected into the floating gate, the memory cell has a first storing state (e.g. the state “1”). Whereas, if the hot carriers are injected into the floating gate, the memory cell has a second storing state (e.g. the state “0”).
Moreover, after the hot carriers are injected into the floating gate, a threshold voltage of the floating gate transistor is subject to a change. Consequently, during a read cycle, the storing state of the memory cell may be realized according to the threshold voltage of the floating gate transistor.
Moreover, during an erase cycle, the hot carriers are rejected from the floating gate.
FIG. 1A is a schematic circuit diagram illustrating a memory cell of a flash memory. As shown in FIG. 1A, the memory cell 11 comprises a select transistor Pa and a floating gate transistor Ma. These two transistors are both p-channel metal-oxide-semiconductor transistors. In addition, the body terminals of these two transistors are connected to a body voltage VBB (e.g. 6V).
The source terminal of the select transistor Pa is connected to a source line to receive a source line voltage VSL. The gate terminal of the select transistor Pa receives a select voltage Vzwl. The source terminal of the floating gate transistor Ma is connected to the drain terminal of the select transistor Pa. The gate terminal of the floating gate transistor Ma receives a control voltage Vzcl. The drain terminal of the floating gate transistor Ma is connected to a bit line BL.
FIG. 1B is a table illustrating associated voltages of the flash memory during a program cycle (PGM) and during an erase cycle (ERS).
During the program cycle, the select voltage Vzwl is 0V. Since the select voltage Vzwl is 0V, it means that the select transistor Pa is selected and turned on. In addition, the source line voltage VSL is 5V, the control voltage Vzcl is 6V, the bit line BL receives 0V, and the body voltage VBB is 6V. Consequently, a program current flows toward the bit line BL. When the program current flows through a channel of the floating gate transistor Ma, the hot carriers are injected into the floating gate. Meanwhile, the program action is completed.
During the erase cycle, the select voltage Vzwl is 0V. Since the select voltage Vzwl is 0V, it means that the select transistor Pa is selected and turned on. In addition, the source line voltage VSL is 6.5V, the control voltage Vzcl is −6.5V, the bit line BL is in a floating state, and the body voltage VBB is 6V. Under this circumstance, since the voltage difference between the gate terminal and the body terminal of the floating gate transistor Ma is 12.5V, the hot carriers are rejected from the floating gate to the body terminal. Meanwhile, the erase action is completed.
From the above discussions, it is necessary to provide higher positive voltages (or lower negative voltages) during the program cycle or the erase cycle of the flash memory. Generally, these voltages are generated by a bias voltage generator.
FIG. 2 is a schematic functional block diagram illustrating a conventional bias voltage generator. As shown in FIG. 2, the conventional bias voltage generator 200 comprises a bandgap reference circuit 210 and a voltage converting circuit 220.
The bandgap reference circuit 210 generates a reference voltage Vref to the voltage converting circuit 220. By the voltage converting circuit 220, the reference voltage Vref is converted into plural output voltages. The output voltages are transmitted to a memory array 230. For example, these output voltages contain the source line voltage VSL, the select voltage Vzwl, the control voltage Vzcl and the body voltage VBB.
Generally, the reference voltage Vref provided by the bandgap reference circuit 210 is stable. In other words, the reference voltage Vref does not vary with the fabricating process, the temperature and the power supply voltage. That is, even if the ambient temperature changes, the reference voltage Vref provided by the bandgap reference circuit 210 is maintained at a fixed voltage value (e.g. 1.163V).
In addition, the voltage converting circuit 220 is a charge pump for enlarging the reference voltage Vref by a specified magnification in order to produce various output voltages. For example, the voltage converting circuit 220 may enlarge the reference voltage Vref by a first magnification in order to produce the source line voltage VSL; and the voltage converting circuit 220 may enlarge the reference voltage Vref by a second magnification in order to produce the control voltage Vzcl. In this way, the bias voltage generator 200 can produce accurate output voltages.